The present invention relates to the field of semiconductor processing, and more particularly, to the detection of silicide failures and the determination of a maximum annealing temperature that prevents silicide failures from occurring.
Fabrication of a semiconductor device and an integrated circuit thereof begins with a semiconductor substrate and typically employs film formation, ion implantation, photolithography, etching, and deposition techniques to form various structural features in or on a semiconductor substrate to attain individual circuit components which are then interconnected to ultimately form an integrated semiconductor device. Escalating requirements for high densification and performance associated with ultra large-scale integration (ULSI) semiconductor devices require smaller design features, and increased transistor and circuit speeds, high reliability and increased manufacturing throughput for competitiveness.
As device dimensions and feature sizes decrease to the deep sub-micron range, performance difficulties escalate, particularly those caused by an increase in a sheet resistance in the contact areas through the source and drain regions and junction leakage as junction layer thickness decreases. To ameliorate the higher electrical resistance caused by shrinking features, the use of self-aligned, highly electrically conductive refractory metal silicides, i.e., xe2x80x9csilicidesxe2x80x9d (derived from self-aligned silicide), has become commonplace in the manufacture of IC semiconductor devices, as for example in the manufacture of MOS type transistors.
Salicide technology comprises forming metal silicide layers on the source/drain regions and/or on the gate electrode of a semiconductor device in a self-aligned manner. A conventional approach to reduce resistivity involves forming a multi-layered structure comprising a low resistance refractory metal silicide layer on a doped polycrystalline silicon, typically referred to as a polycide. Salicide technology reduces parasitic sheet and contact resistance in the source and drain and diffusion layers and the gate electrode that results from scaling down the source and drain junctions in polycrystalline silicon line width.
Refractory metals commonly employed in salicide processing include platinum (Pt), titanium (Ti), and cobolt (Co), each of which forms very low resistivity phases with silicon (Si), e.g., PtSi2, TiSi2, and CoSi2. In practice, the refractory metal is deposited at a uniform thickness over all exposed surface features of a Si wafer, preferably by means of physical vapor deposition (xe2x80x9cPVDxe2x80x9d) process, e.g. sputtering from a target utilizing an ultra high-vacuum, multi-chamber DC magnetron or RF sputtering system. Such PVD tools are commercially available, as for example by Applied Materials, Inc., of Santa Clara, Calif.; and by MRC of Gilbert, Ariz.
In MOS transistor formation, deposition is generally performed both after a gate etch and after source/drain formation. After deposition, the refractory metal layer blankets the top surface of the gate electrode, typically formed of a heavily-doped polysilicon, the silicon oxide, nitride, or oxynitride spacer walls on the opposing side surfaces of the gate electrode, silicon oxide isolation regions formed in the silicon substrate between adjacent active device regions, and the exposed surfaces of the substrate where the source and drain regions are formed or will subsequently be formed. As a result of thermal processing, e.g., a rapid thermal annealing (xe2x80x9cRTAxe2x80x9d) performed in an inert atmosphere, the refractory metal layer reacts with the source and drain surfaces and the top surface of the polysilicon gate metal silicide layers. Unreacted portions of the refractory metal layer, e.g., on the silicon oxide, nitride, or oxynitride spacer walls and the silicon oxide isolation regions, are then removed, as by a wet chemical etching process selective to metal silicide portions.
The RTA step used to anneal refractory metal and silicon to form silicide is very critical. When the temperature of the RTA is too low, or the process time is too short, incomplete silicide formation may result. This leads to very poor transistor performance. On the other hand, if the RTA is too high, transistor leakage and short failures may occur. These leakage or short failures are due to the creeping of silicide from gate to source/drain areas. It is therefore important to determine the highest possible RTA temperature for a silicide process that does not produce transistor short failures.
The conventional process for determining the highest possible RTA temperature involves the formation of silicide on a semiconductor wafer and then performing scanning electron microscope (SEM) inspection of cross-sectioned samples. The SEM inspection reveals leakage or shorts of the transistor. Unfortunately, a relatively long time is required to prepare the sample and locate the failure sites. Furthermore, the number of samples that can be prepared for examination is limited.
There is a need for a method of monitoring silicide failures of a semiconductor wafer, and also a need to determine the highest possible RTA temperature to form silicide without creating transistor short failures.
In certain embodiments of the invention, a method of determining a rapid thermal anneal (RTA) for a silicide process is provided. The method comprises the steps of forming a plurality of semiconductor wafers, each wafer having a gate oxide capacitor set. Silicide is formed on each wafer, employing a different RTA for each wafer. The breakdown voltages of the gate oxide capacitor set of each wafer are measured. The wafer is identified which has the highest RTA among those wafers that have a gate oxide capacitor set with measured breakdown voltage greater than a specified threshold. The RTA for the silicide process is the RTA for the identified wafer.
Another aspect of the present invention provides a method of determining a maximum process temperature for a silicide process and comprises the steps of forming silicide at different process temperatures on respective semiconductor wafer. The breakdown voltages on gate oxide capacitors are measured on the semiconductor wafers. The semiconductor wafer with silicide formed at the highest process temperature and measured breakdown voltages above a threshold value is identified. The maximum process temperature for the silicide process is equal to the process temperature for the identified semiconductor wafer.
The present invention takes advantage of the discovery by the present inventors that the number of leakage or a silicide short failures of certain capacitors is directly related to RTA temperatures. For example, a P-channel capacitor with gate edge structure is extremely sensitive to silicide failures or bridging caused by excessive RTA temperature. In other words, the higher the RTA temperature, the greater the number of short failures of P-channel gate edge capacitors (or gate oxide capacitors). Based on the correlation of the P-channel gate edge capacitor failures in the RTA temperatures, the optimum RTA temperature is readily determined. Furthermore, the present invention can also be used to monitor the uniformity of the RTA equipment.
The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.